0x40012000: Analog-to-digital converter
84/84 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | SR | ||||||||||||||||||||||||||||||||
| 0x4 | CR1 | ||||||||||||||||||||||||||||||||
| 0x8 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | SMPR1 | ||||||||||||||||||||||||||||||||
| 0x10 | SMPR2 | ||||||||||||||||||||||||||||||||
| 0x14 | JOFR[1] | ||||||||||||||||||||||||||||||||
| 0x18 | JOFR[2] | ||||||||||||||||||||||||||||||||
| 0x1c | JOFR[3] | ||||||||||||||||||||||||||||||||
| 0x20 | JOFR[4] | ||||||||||||||||||||||||||||||||
| 0x24 | HTR | ||||||||||||||||||||||||||||||||
| 0x28 | LTR | ||||||||||||||||||||||||||||||||
| 0x2c | SQR1 | ||||||||||||||||||||||||||||||||
| 0x30 | SQR2 | ||||||||||||||||||||||||||||||||
| 0x34 | SQR3 | ||||||||||||||||||||||||||||||||
| 0x38 | JSQR | ||||||||||||||||||||||||||||||||
| 0x3c | JDR[1] | ||||||||||||||||||||||||||||||||
| 0x40 | JDR[2] | ||||||||||||||||||||||||||||||||
| 0x44 | JDR[3] | ||||||||||||||||||||||||||||||||
| 0x48 | JDR[4] | ||||||||||||||||||||||||||||||||
| 0x4c | DR | ||||||||||||||||||||||||||||||||
injected channel data offset register x
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x1c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
injected channel data offset register x
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JOFFSET
rw |
|||||||||||||||
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HT
rw |
|||||||||||||||
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT
rw |
|||||||||||||||
injected data register x
Offset: 0x3c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x44, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
injected data register x
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
JDATA
r |
|||||||||||||||
regular data register
Offset: 0x4c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
r |
|||||||||||||||
0x40012300: ADC common registers
9/9 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CSR | ||||||||||||||||||||||||||||||||
| 0x4 | CCR | ||||||||||||||||||||||||||||||||
ADC common control register
Offset: 0x4, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TSVREFE
rw |
VBATE
rw |
ADCPRE
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x40023000: Cryptographic processor
3/3 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | DR | ||||||||||||||||||||||||||||||||
| 0x4 | IDR | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
Data register
Offset: 0x0, reset: 0xFFFFFFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Independent Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IDR
rw |
|||||||||||||||
Control register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RESET
w |
|||||||||||||||
0x40007400: Digital-to-analog converter
34/34 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | SWTRIGR | ||||||||||||||||||||||||||||||||
| 0x8 | DHR12R1 | ||||||||||||||||||||||||||||||||
| 0xc | DHR12L1 | ||||||||||||||||||||||||||||||||
| 0x10 | DHR8R1 | ||||||||||||||||||||||||||||||||
| 0x14 | DHR12R2 | ||||||||||||||||||||||||||||||||
| 0x18 | DHR12L2 | ||||||||||||||||||||||||||||||||
| 0x1c | DHR8R2 | ||||||||||||||||||||||||||||||||
| 0x20 | DHR12RD | ||||||||||||||||||||||||||||||||
| 0x24 | DHR12LD | ||||||||||||||||||||||||||||||||
| 0x28 | DHR8RD | ||||||||||||||||||||||||||||||||
| 0x2c | DOR1 | ||||||||||||||||||||||||||||||||
| 0x30 | DOR2 | ||||||||||||||||||||||||||||||||
| 0x34 | SR | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, reset: 0x00000000, access: read-write
16/16 fields covered.
Bits 19-21: DAC channel2 trigger selection.
Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger
software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWTRIG2
w |
SWTRIG1
w |
||||||||||||||
channel1 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 12-bit left aligned data holding register
Offset: 0xc, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel1 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
channel2 12-bit right aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
channel2 8-bit right-aligned data holding register
Offset: 0x1c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
DACC1DHR
rw |
||||||||||||||
channel1 data output register
Offset: 0x2c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DOR
r |
|||||||||||||||
channel2 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DOR
r |
|||||||||||||||
status register
Offset: 0x34, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAUDR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAUDR1
rw |
|||||||||||||||
0xe0042000: Debug support
2/21 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | IDCODE | ||||||||||||||||||||||||||||||||
| 0x4 | CR | ||||||||||||||||||||||||||||||||
| 0x8 | APB1_FZ | ||||||||||||||||||||||||||||||||
| 0xc | APB2_FZ | ||||||||||||||||||||||||||||||||
IDCODE
Offset: 0x0, reset: 0x10006411, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REV_ID
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEV_ID
r |
|||||||||||||||
Control Register
Offset: 0x4, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRACE_MODE
rw |
TRACE_IOEN
rw |
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG_SLEEP
rw |
|||||||||||
Debug MCU APB1 Freeze registe
Offset: 0x8, reset: 0x00000000, access: read-write
0/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_I2C3SMBUS_TIMEOUT
rw |
DBG_I2C2_SMBUS_TIMEOUT
rw |
DBG_I2C1_SMBUS_TIMEOUT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_Stop
rw |
DBG_TIM5_STOP
rw |
DBG_TIM4_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIM2_STOP
rw |
|||||||||
Debug MCU APB2 Freeze registe
Offset: 0xc, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_TIM11_STOP
rw |
DBG_TIM10_STOP
rw |
DBG_TIM9_STOP
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_TIM1_STOP
rw |
|||||||||||||||
0x40026000: DMA controller
272/296 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | LISR | ||||||||||||||||||||||||||||||||
| 0x4 | HISR | ||||||||||||||||||||||||||||||||
| 0x8 | LIFCR | ||||||||||||||||||||||||||||||||
| 0xc | HIFCR | ||||||||||||||||||||||||||||||||
| 0x10 | CR [0] | ||||||||||||||||||||||||||||||||
| 0x14 | NDTR [0] | ||||||||||||||||||||||||||||||||
| 0x18 | PAR [0] | ||||||||||||||||||||||||||||||||
| 0x1c | M0AR [0] | ||||||||||||||||||||||||||||||||
| 0x20 | M1AR [0] | ||||||||||||||||||||||||||||||||
| 0x24 | FCR [0] | ||||||||||||||||||||||||||||||||
| 0x28 | CR [1] | ||||||||||||||||||||||||||||||||
| 0x2c | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x30 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x34 | M0AR [1] | ||||||||||||||||||||||||||||||||
| 0x38 | M1AR [1] | ||||||||||||||||||||||||||||||||
| 0x3c | FCR [1] | ||||||||||||||||||||||||||||||||
| 0x40 | CR [2] | ||||||||||||||||||||||||||||||||
| 0x44 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x48 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x4c | M0AR [2] | ||||||||||||||||||||||||||||||||
| 0x50 | M1AR [2] | ||||||||||||||||||||||||||||||||
| 0x54 | FCR [2] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x64 | M0AR [3] | ||||||||||||||||||||||||||||||||
| 0x68 | M1AR [3] | ||||||||||||||||||||||||||||||||
| 0x6c | FCR [3] | ||||||||||||||||||||||||||||||||
| 0x70 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x74 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x78 | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x7c | M0AR [4] | ||||||||||||||||||||||||||||||||
| 0x80 | M1AR [4] | ||||||||||||||||||||||||||||||||
| 0x84 | FCR [4] | ||||||||||||||||||||||||||||||||
| 0x88 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x8c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x90 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x94 | M0AR [5] | ||||||||||||||||||||||||||||||||
| 0x98 | M1AR [5] | ||||||||||||||||||||||||||||||||
| 0x9c | FCR [5] | ||||||||||||||||||||||||||||||||
| 0xa0 | CR [6] | ||||||||||||||||||||||||||||||||
| 0xa4 | NDTR [6] | ||||||||||||||||||||||||||||||||
| 0xa8 | PAR [6] | ||||||||||||||||||||||||||||||||
| 0xac | M0AR [6] | ||||||||||||||||||||||||||||||||
| 0xb0 | M1AR [6] | ||||||||||||||||||||||||||||||||
| 0xb4 | FCR [6] | ||||||||||||||||||||||||||||||||
| 0xb8 | CR [7] | ||||||||||||||||||||||||||||||||
| 0xbc | NDTR [7] | ||||||||||||||||||||||||||||||||
| 0xc0 | PAR [7] | ||||||||||||||||||||||||||||||||
| 0xc4 | M0AR [7] | ||||||||||||||||||||||||||||||||
| 0xc8 | M1AR [7] | ||||||||||||||||||||||||||||||||
| 0xcc | FCR [7] | ||||||||||||||||||||||||||||||||
stream x number of data register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x1c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x20, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x24, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x30, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x3c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x44, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x48, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x4c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x54, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x5c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x60, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x64, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x68, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x6c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x74, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x78, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x7c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x84, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x8c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x90, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x94, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x98, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x9c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0xa4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0xa8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0xac, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0xb0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0xb4, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0xbc, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0xc0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0xc4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0xc8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0xcc, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
0x40026400: DMA controller
272/296 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | LISR | ||||||||||||||||||||||||||||||||
| 0x4 | HISR | ||||||||||||||||||||||||||||||||
| 0x8 | LIFCR | ||||||||||||||||||||||||||||||||
| 0xc | HIFCR | ||||||||||||||||||||||||||||||||
| 0x10 | CR [0] | ||||||||||||||||||||||||||||||||
| 0x14 | NDTR [0] | ||||||||||||||||||||||||||||||||
| 0x18 | PAR [0] | ||||||||||||||||||||||||||||||||
| 0x1c | M0AR [0] | ||||||||||||||||||||||||||||||||
| 0x20 | M1AR [0] | ||||||||||||||||||||||||||||||||
| 0x24 | FCR [0] | ||||||||||||||||||||||||||||||||
| 0x28 | CR [1] | ||||||||||||||||||||||||||||||||
| 0x2c | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x30 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x34 | M0AR [1] | ||||||||||||||||||||||||||||||||
| 0x38 | M1AR [1] | ||||||||||||||||||||||||||||||||
| 0x3c | FCR [1] | ||||||||||||||||||||||||||||||||
| 0x40 | CR [2] | ||||||||||||||||||||||||||||||||
| 0x44 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x48 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x4c | M0AR [2] | ||||||||||||||||||||||||||||||||
| 0x50 | M1AR [2] | ||||||||||||||||||||||||||||||||
| 0x54 | FCR [2] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x64 | M0AR [3] | ||||||||||||||||||||||||||||||||
| 0x68 | M1AR [3] | ||||||||||||||||||||||||||||||||
| 0x6c | FCR [3] | ||||||||||||||||||||||||||||||||
| 0x70 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x74 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x78 | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x7c | M0AR [4] | ||||||||||||||||||||||||||||||||
| 0x80 | M1AR [4] | ||||||||||||||||||||||||||||||||
| 0x84 | FCR [4] | ||||||||||||||||||||||||||||||||
| 0x88 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x8c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x90 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x94 | M0AR [5] | ||||||||||||||||||||||||||||||||
| 0x98 | M1AR [5] | ||||||||||||||||||||||||||||||||
| 0x9c | FCR [5] | ||||||||||||||||||||||||||||||||
| 0xa0 | CR [6] | ||||||||||||||||||||||||||||||||
| 0xa4 | NDTR [6] | ||||||||||||||||||||||||||||||||
| 0xa8 | PAR [6] | ||||||||||||||||||||||||||||||||
| 0xac | M0AR [6] | ||||||||||||||||||||||||||||||||
| 0xb0 | M1AR [6] | ||||||||||||||||||||||||||||||||
| 0xb4 | FCR [6] | ||||||||||||||||||||||||||||||||
| 0xb8 | CR [7] | ||||||||||||||||||||||||||||||||
| 0xbc | NDTR [7] | ||||||||||||||||||||||||||||||||
| 0xc0 | PAR [7] | ||||||||||||||||||||||||||||||||
| 0xc4 | M0AR [7] | ||||||||||||||||||||||||||||||||
| 0xc8 | M1AR [7] | ||||||||||||||||||||||||||||||||
| 0xcc | FCR [7] | ||||||||||||||||||||||||||||||||
stream x number of data register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x1c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x20, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x24, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x30, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x3c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x44, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x48, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x4c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x54, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x5c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x60, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x64, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x68, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x6c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x74, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x78, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x7c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x84, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0x8c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0x90, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0x94, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0x98, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0x9c, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0xa4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0xa8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0xac, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0xb0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0xb4, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
stream x number of data register
Offset: 0xbc, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
stream x peripheral address register
Offset: 0xc0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
stream x memory 0 address register
Offset: 0xc4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M0A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M0A
rw |
|||||||||||||||
stream x memory 1 address register
Offset: 0xc8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
M1A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
M1A
rw |
|||||||||||||||
stream x FIFO control register
Offset: 0xcc, reset: 0x00000021, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FEIE
rw |
FS
r |
DMDIS
rw |
FTH
rw |
||||||||||||
0x40013c00: External interrupt/event controller
138/138 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | IMR | ||||||||||||||||||||||||||||||||
| 0x4 | EMR | ||||||||||||||||||||||||||||||||
| 0x8 | RTSR | ||||||||||||||||||||||||||||||||
| 0xc | FTSR | ||||||||||||||||||||||||||||||||
| 0x10 | SWIER | ||||||||||||||||||||||||||||||||
| 0x14 | PR |
Software interrupt event register (EXTI_SWIER)
Offset: 0x10, reset: 0x00000000, access: read-write
23/23 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SWIER22
rw |
SWIER21
rw |
SWIER20
rw |
SWIER19
rw |
SWIER18
rw |
SWIER17
rw |
SWIER16
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWIER15
rw |
SWIER14
rw |
SWIER13
rw |
SWIER12
rw |
SWIER11
rw |
SWIER10
rw |
SWIER9
rw |
SWIER8
rw |
SWIER7
rw |
SWIER6
rw |
SWIER5
rw |
SWIER4
rw |
SWIER3
rw |
SWIER2
rw |
SWIER1
rw |
SWIER0
rw |
0x40023c00: FLASH
18/33 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ACR | ||||||||||||||||||||||||||||||||
| 0x4 | KEYR | ||||||||||||||||||||||||||||||||
| 0x8 | OPTKEYR | ||||||||||||||||||||||||||||||||
| 0xc | SR | ||||||||||||||||||||||||||||||||
| 0x10 | CR | ||||||||||||||||||||||||||||||||
| 0x14 | OPTCR | ||||||||||||||||||||||||||||||||
Flash access control register
Offset: 0x0, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-3: Latency.
Allowed values:
0: WS0: 0 wait states
1: WS1: 1 wait states
2: WS2: 2 wait states
3: WS3: 3 wait states
4: WS4: 4 wait states
5: WS5: 5 wait states
6: WS6: 6 wait states
7: WS7: 7 wait states
8: WS8: 8 wait states
9: WS9: 9 wait states
10: WS10: 10 wait states
11: WS11: 11 wait states
12: WS12: 12 wait states
13: WS13: 13 wait states
14: WS14: 14 wait states
15: WS15: 15 wait states
Flash key register
Offset: 0x4, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
KEY
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Flash option key register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OPTKEY
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OPTKEY
w |
|||||||||||||||
Flash option control register
Offset: 0x14, reset: 0x7FFFAAED, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SPRMOD
rw |
nWRP
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDP
rw |
nRST_STDBY
rw |
nRST_STOP
rw |
WDG_SW
rw |
BOR_LEV
rw |
OPTSTRT
rw |
OPTLOCK
rw |
|||||||||
0x40006000: Inter-integrated circuit
75/76 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x00000000, access: read-write
19/20 fields covered.
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xc, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0xe000ef34: Floting point unit
0/24 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | FPCCR | ||||||||||||||||||||||||||||||||
| 0x4 | FPCAR | ||||||||||||||||||||||||||||||||
| 0x8 | FPSCR | ||||||||||||||||||||||||||||||||
Floating-point context address register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDRESS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDRESS
rw |
|||||||||||||||
0xe000ed88: Floating point unit CPACR
0/1 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CPACR | ||||||||||||||||||||||||||||||||
Coprocessor access control register
Offset: 0x0, reset: 0x0000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x40020000: General-purpose I/Os
161/161 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40020400: General-purpose I/Os
161/161 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40020800: General-purpose I/Os
161/161 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40021c00: General-purpose I/Os
161/161 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40005400: Inter-integrated circuit
53/53 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | DR | ||||||||||||||||||||||||||||||||
| 0x14 | SR1 | ||||||||||||||||||||||||||||||||
| 0x18 | SR2 | ||||||||||||||||||||||||||||||||
| 0x1c | CCR | ||||||||||||||||||||||||||||||||
| 0x20 | TRISE | ||||||||||||||||||||||||||||||||
| 0x24 | FLTR | ||||||||||||||||||||||||||||||||
Own address register 1
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDMODE
rw |
ADD
rw |
||||||||||||||
Own address register 2
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADD2
rw |
ENDUAL
rw |
||||||||||||||
Data register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Status register 2
Offset: 0x18, reset: 0x0000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
DUALF
r |
SMBHOST
r |
SMBDEFAULT
r |
GENCALL
r |
TRA
r |
BUSY
r |
MSL
r |
||||||||
Clock control register
Offset: 0x1c, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F_S
rw |
DUTY
rw |
CCR
rw |
|||||||||||||
TRISE register
Offset: 0x20, reset: 0x0002, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRISE
rw |
|||||||||||||||
FLTR register
Offset: 0x24, reset: 0, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ANOFF
rw |
DNF
rw |
||||||||||||||
Bits 0-3: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
0x40005800: Inter-integrated circuit
53/53 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | DR | ||||||||||||||||||||||||||||||||
| 0x14 | SR1 | ||||||||||||||||||||||||||||||||
| 0x18 | SR2 | ||||||||||||||||||||||||||||||||
| 0x1c | CCR | ||||||||||||||||||||||||||||||||
| 0x20 | TRISE | ||||||||||||||||||||||||||||||||
| 0x24 | FLTR | ||||||||||||||||||||||||||||||||
Own address register 1
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDMODE
rw |
ADD
rw |
||||||||||||||
Own address register 2
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADD2
rw |
ENDUAL
rw |
||||||||||||||
Data register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Status register 2
Offset: 0x18, reset: 0x0000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
DUALF
r |
SMBHOST
r |
SMBDEFAULT
r |
GENCALL
r |
TRA
r |
BUSY
r |
MSL
r |
||||||||
Clock control register
Offset: 0x1c, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F_S
rw |
DUTY
rw |
CCR
rw |
|||||||||||||
TRISE register
Offset: 0x20, reset: 0x0002, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRISE
rw |
|||||||||||||||
FLTR register
Offset: 0x24, reset: 0, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ANOFF
rw |
DNF
rw |
||||||||||||||
Bits 0-3: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
0x40003000: Independent watchdog
5/5 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | KR | ||||||||||||||||||||||||||||||||
| 0x4 | PR | ||||||||||||||||||||||||||||||||
| 0x8 | RLR | ||||||||||||||||||||||||||||||||
| 0xc | SR | ||||||||||||||||||||||||||||||||
Key register
Offset: 0x0, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Prescaler register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR
rw |
|||||||||||||||
Reload register
Offset: 0x8, reset: 0x00000FFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RL
rw |
|||||||||||||||
Status register
Offset: 0xc, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RVU
r |
PVU
r |
||||||||||||||
0x40002400: Low power timer
8/41 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | ICR | ||||||||||||||||||||||||||||||||
| 0x8 | IER | ||||||||||||||||||||||||||||||||
| 0xc | CFGR | ||||||||||||||||||||||||||||||||
| 0x10 | CR | ||||||||||||||||||||||||||||||||
| 0x14 | CMP | ||||||||||||||||||||||||||||||||
| 0x18 | ARR | ||||||||||||||||||||||||||||||||
| 0x1c | CNT | ||||||||||||||||||||||||||||||||
| 0x20 | OPTR | ||||||||||||||||||||||||||||||||
Control Register
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNTSTRT
rw |
SNGSTRT
rw |
ENABLE
rw |
|||||||||||||
Compare Register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP
rw |
|||||||||||||||
Autoreload Register
Offset: 0x18, reset: 0x00000001, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
Counter Register
Offset: 0x1c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
r |
|||||||||||||||
Option Register
Offset: 0x20, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OR
rw |
|||||||||||||||
0xe000ed90: Memory protection unit
6/19 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | TYPER | ||||||||||||||||||||||||||||||||
| 0x4 | CTRL | ||||||||||||||||||||||||||||||||
| 0x8 | RNR | ||||||||||||||||||||||||||||||||
| 0xc | RBAR | ||||||||||||||||||||||||||||||||
| 0x10 | RASR | ||||||||||||||||||||||||||||||||
MPU type register
Offset: 0x0, reset: 0X00000800, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IREGION
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DREGION
r |
SEPARATE
r |
||||||||||||||
MPU control register
Offset: 0x4, reset: 0X00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRIVDEFENA
r |
HFNMIENA
r |
ENABLE
r |
|||||||||||||
MPU region number register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REGION
rw |
|||||||||||||||
MPU region base address register
Offset: 0xc, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ADDR
rw |
VALID
rw |
REGION
rw |
|||||||||||||
0xe000e100: Nested Vectored Interrupt Controller
3/95 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISER0 | ||||||||||||||||||||||||||||||||
| 0x4 | ISER1 | ||||||||||||||||||||||||||||||||
| 0x8 | ISER2 | ||||||||||||||||||||||||||||||||
| 0x80 | ICER0 | ||||||||||||||||||||||||||||||||
| 0x84 | ICER1 | ||||||||||||||||||||||||||||||||
| 0x88 | ICER2 | ||||||||||||||||||||||||||||||||
| 0x100 | ISPR0 | ||||||||||||||||||||||||||||||||
| 0x104 | ISPR1 | ||||||||||||||||||||||||||||||||
| 0x108 | ISPR2 | ||||||||||||||||||||||||||||||||
| 0x180 | ICPR0 | ||||||||||||||||||||||||||||||||
| 0x184 | ICPR1 | ||||||||||||||||||||||||||||||||
| 0x188 | ICPR2 | ||||||||||||||||||||||||||||||||
| 0x200 | IABR0 | ||||||||||||||||||||||||||||||||
| 0x204 | IABR1 | ||||||||||||||||||||||||||||||||
| 0x208 | IABR2 | ||||||||||||||||||||||||||||||||
| 0x300 | IPR0 | ||||||||||||||||||||||||||||||||
| 0x304 | IPR1 | ||||||||||||||||||||||||||||||||
| 0x308 | IPR2 | ||||||||||||||||||||||||||||||||
| 0x30c | IPR3 | ||||||||||||||||||||||||||||||||
| 0x310 | IPR4 | ||||||||||||||||||||||||||||||||
| 0x314 | IPR5 | ||||||||||||||||||||||||||||||||
| 0x318 | IPR6 | ||||||||||||||||||||||||||||||||
| 0x31c | IPR7 | ||||||||||||||||||||||||||||||||
| 0x320 | IPR8 | ||||||||||||||||||||||||||||||||
| 0x324 | IPR9 | ||||||||||||||||||||||||||||||||
| 0x328 | IPR10 | ||||||||||||||||||||||||||||||||
| 0x32c | IPR11 | ||||||||||||||||||||||||||||||||
| 0x330 | IPR12 | ||||||||||||||||||||||||||||||||
| 0x334 | IPR13 | ||||||||||||||||||||||||||||||||
| 0x338 | IPR14 | ||||||||||||||||||||||||||||||||
| 0x33c | IPR15 | ||||||||||||||||||||||||||||||||
| 0x340 | IPR16 | ||||||||||||||||||||||||||||||||
| 0x344 | IPR17 | ||||||||||||||||||||||||||||||||
| 0x348 | IPR18 | ||||||||||||||||||||||||||||||||
| 0x34c | IPR19 | ||||||||||||||||||||||||||||||||
Interrupt Set-Enable Register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Set-Enable Register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x84, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Clear-Enable Register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRENA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRENA
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x100, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x104, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Set-Pending Register
Offset: 0x108, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SETPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SETPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x180, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x184, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Clear-Pending Register
Offset: 0x188, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CLRPEND
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLRPEND
rw |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x200, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x204, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Active Bit Register
Offset: 0x208, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ACTIVE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ACTIVE
r |
|||||||||||||||
Interrupt Priority Register
Offset: 0x300, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x304, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x308, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x30c, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x310, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x314, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x318, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x31c, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x320, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x324, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x328, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x32c, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x330, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x334, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x338, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x33c, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x340, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x344, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x348, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
Interrupt Priority Register
Offset: 0x34c, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IPR_N1
rw |
IPR_N0
rw |
||||||||||||||
0xe000ef00: Nested vectored interrupt controller
0/1 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | STIR | ||||||||||||||||||||||||||||||||
Software trigger interrupt register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
INTID
rw |
|||||||||||||||
0x40007000: Power control
4/19 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CSR | ||||||||||||||||||||||||||||||||
0x40023800: Reset and clock control
162/162 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | PLLCFGR | ||||||||||||||||||||||||||||||||
| 0x8 | CFGR | ||||||||||||||||||||||||||||||||
| 0xc | CIR | ||||||||||||||||||||||||||||||||
| 0x10 | AHB1RSTR | ||||||||||||||||||||||||||||||||
| 0x20 | APB1RSTR | ||||||||||||||||||||||||||||||||
| 0x24 | APB2RSTR | ||||||||||||||||||||||||||||||||
| 0x30 | AHB1ENR | ||||||||||||||||||||||||||||||||
| 0x40 | APB1ENR | ||||||||||||||||||||||||||||||||
| 0x44 | APB2ENR | ||||||||||||||||||||||||||||||||
| 0x50 | AHB1LPENR | ||||||||||||||||||||||||||||||||
| 0x60 | APB1LPENR | ||||||||||||||||||||||||||||||||
| 0x64 | APB2LPENR | ||||||||||||||||||||||||||||||||
| 0x70 | BDCR | ||||||||||||||||||||||||||||||||
| 0x74 | CSR | ||||||||||||||||||||||||||||||||
| 0x80 | SSCGR | ||||||||||||||||||||||||||||||||
| 0x8c | DCKCFGR | ||||||||||||||||||||||||||||||||
| 0x94 | DCKCFGR2 | ||||||||||||||||||||||||||||||||
clock configuration register
Offset: 0x8, reset: 0x00000000, access: Unspecified
12/12 fields covered.
Bits 4-7: AHB prescaler.
Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
APB1 peripheral clock enable in low power mode register
Offset: 0x60, reset: 0x36FEC9FF, access: read-write
12/12 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACLPEN
rw |
PWRLPEN
rw |
FMPI2C1LPEN
rw |
I2C2LPEN
rw |
I2C1LPEN
rw |
USART2LPEN
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI2LPEN
rw |
WWDGLPEN
rw |
RTCAPBLPEN
rw |
LPTIM1LPEN
rw |
TIM6LPEN
rw |
TIM5LPEN
rw |
||||||||||
APB2 peripheral clock enabled in low power mode register
Offset: 0x64, reset: 0x00075F33, access: read-write
11/11 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SPI5LPEN
rw |
TIM11LPEN
rw |
TIM9LPEN
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTITLPEN
rw |
SYSCFGLPEN
rw |
SPI1LPEN
rw |
SDIOLPEN
rw |
ADC1LPEN
rw |
USART6LPEN
rw |
USART1LPEN
rw |
TIM1LPEN
rw |
||||||||
DCKCFGR register
Offset: 0x8c, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
I2SSRC
rw |
TIMPRE
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCKCFGR2 register
Offset: 0x94, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LPTIM1SEL
rw |
FMPI2C1SEL
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x40080000: Random number generator
4/8 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | SR | ||||||||||||||||||||||||||||||||
| 0x8 | DR | ||||||||||||||||||||||||||||||||
control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IE
rw |
RNGEN
rw |
||||||||||||||
data register
Offset: 0x8, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RNDATA
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RNDATA
r |
|||||||||||||||
0x40002800: Real-time clock
126/142 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | TR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
| 0xc | ISR | ||||||||||||||||||||||||||||||||
| 0x10 | PRER | ||||||||||||||||||||||||||||||||
| 0x14 | WUTR | ||||||||||||||||||||||||||||||||
| 0x18 | CALIBR | ||||||||||||||||||||||||||||||||
| 0x1c | ALRM[A]R | ||||||||||||||||||||||||||||||||
| 0x20 | ALRM[B]R | ||||||||||||||||||||||||||||||||
| 0x24 | WPR | ||||||||||||||||||||||||||||||||
| 0x28 | SSR | ||||||||||||||||||||||||||||||||
| 0x2c | SHIFTR | ||||||||||||||||||||||||||||||||
| 0x30 | TSTR | ||||||||||||||||||||||||||||||||
| 0x34 | TSDR | ||||||||||||||||||||||||||||||||
| 0x38 | TSSSR | ||||||||||||||||||||||||||||||||
| 0x3c | CALR | ||||||||||||||||||||||||||||||||
| 0x40 | TAFCR | ||||||||||||||||||||||||||||||||
| 0x44 | ALRM[A]SSR | ||||||||||||||||||||||||||||||||
| 0x48 | ALRM[B]SSR | ||||||||||||||||||||||||||||||||
| 0x50 | BKP[0]R | ||||||||||||||||||||||||||||||||
| 0x54 | BKP[1]R | ||||||||||||||||||||||||||||||||
| 0x58 | BKP[2]R | ||||||||||||||||||||||||||||||||
| 0x5c | BKP[3]R | ||||||||||||||||||||||||||||||||
| 0x60 | BKP[4]R | ||||||||||||||||||||||||||||||||
| 0x64 | BKP[5]R | ||||||||||||||||||||||||||||||||
| 0x68 | BKP[6]R | ||||||||||||||||||||||||||||||||
| 0x6c | BKP[7]R | ||||||||||||||||||||||||||||||||
| 0x70 | BKP[8]R | ||||||||||||||||||||||||||||||||
| 0x74 | BKP[9]R | ||||||||||||||||||||||||||||||||
| 0x78 | BKP[10]R | ||||||||||||||||||||||||||||||||
| 0x7c | BKP[11]R | ||||||||||||||||||||||||||||||||
| 0x80 | BKP[12]R | ||||||||||||||||||||||||||||||||
| 0x84 | BKP[13]R | ||||||||||||||||||||||||||||||||
| 0x88 | BKP[14]R | ||||||||||||||||||||||||||||||||
| 0x8c | BKP[15]R | ||||||||||||||||||||||||||||||||
| 0x90 | BKP[16]R | ||||||||||||||||||||||||||||||||
| 0x94 | BKP[17]R | ||||||||||||||||||||||||||||||||
| 0x98 | BKP[18]R | ||||||||||||||||||||||||||||||||
| 0x9c | BKP[19]R | ||||||||||||||||||||||||||||||||
control register
Offset: 0x8, reset: 0x00000000, access: read-write
20/21 fields covered.
Bits 0-2: Wakeup clock selection.
Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
Bit 5: Bypass the shadow registers.
Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
prescaler register
Offset: 0x10, reset: 0x007F00FF, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PREDIV_A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PREDIV_S
rw |
|||||||||||||||
wakeup timer register
Offset: 0x14, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUT
rw |
|||||||||||||||
calibration register
Offset: 0x18, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DCS
rw |
DC
rw |
||||||||||||||
write protection register
Offset: 0x24, reset: 0x00000000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
sub second register
Offset: 0x28, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
shift control register
Offset: 0x2c, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD1S
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SUBFS
w |
|||||||||||||||
timestamp sub second register
Offset: 0x38, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
calibration register
Offset: 0x3c, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALP
rw |
CALW8
rw |
CALW16
rw |
CALM
rw |
||||||||||||
tamper and alternate function configuration register
Offset: 0x40, reset: 0x00000000, access: read-write
0/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ALARMOUTTYPE
rw |
TSINSEL
rw |
TAMP1INSEL
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
TAMPTS
rw |
TAMP2TRG
rw |
TAMP2E
rw |
TAMPIE
rw |
TAMP1TRG
rw |
TAMP1E
rw |
||||||
Alarm sub-second register
Offset: 0x44, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
Alarm sub-second register
Offset: 0x48, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
backup register
Offset: 0x50, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x54, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x58, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x5c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x60, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x64, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x68, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x6c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x70, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x74, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x78, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x7c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x80, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x84, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x88, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x8c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x90, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x94, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x98, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
backup register
Offset: 0x9c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
0xe000ed00: System control block
5/74 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CPUID | ||||||||||||||||||||||||||||||||
| 0x4 | ICSR | ||||||||||||||||||||||||||||||||
| 0x8 | VTOR | ||||||||||||||||||||||||||||||||
| 0xc | AIRCR | ||||||||||||||||||||||||||||||||
| 0x10 | SCR | ||||||||||||||||||||||||||||||||
| 0x14 | CCR | ||||||||||||||||||||||||||||||||
| 0x18 | SHPR1 | ||||||||||||||||||||||||||||||||
| 0x1c | SHPR2 | ||||||||||||||||||||||||||||||||
| 0x20 | SHPR3 | ||||||||||||||||||||||||||||||||
| 0x24 | SHCRS | ||||||||||||||||||||||||||||||||
| 0x28 | CFSR_UFSR_BFSR_MMFSR | ||||||||||||||||||||||||||||||||
| 0x2c | HFSR | ||||||||||||||||||||||||||||||||
| 0x34 | MMFAR | ||||||||||||||||||||||||||||||||
| 0x38 | BFAR | ||||||||||||||||||||||||||||||||
| 0x3c | AFSR | ||||||||||||||||||||||||||||||||
CPUID base register
Offset: 0x0, reset: 0x410FC241, access: read-only
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Implementer
r |
Variant
r |
Constant
r |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PartNo
r |
Revision
r |
||||||||||||||
Interrupt control and state register
Offset: 0x4, reset: 0x00000000, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
rw |
PENDSTSET
rw |
PENDSTCLR
rw |
ISRPENDING
rw |
VECTPENDING
rw |
|||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTPENDING
rw |
RETTOBASE
rw |
VECTACTIVE
rw |
|||||||||||||
Vector table offset register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TBLOFF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TBLOFF
rw |
|||||||||||||||
Application interrupt and reset control register
Offset: 0xc, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VECTKEYSTAT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ENDIANESS
rw |
PRIGROUP
rw |
SYSRESETREQ
rw |
VECTCLRACTIVE
rw |
VECTRESET
rw |
|||||||||||
System control register
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SEVEONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
|||||||||||||
Configuration and control register
Offset: 0x14, reset: 0x00000000, access: read-write
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN__TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
||||||||||
System handler priority registers
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_6
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRI_5
rw |
PRI_4
rw |
||||||||||||||
System handler priority registers
Offset: 0x1c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_11
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler priority registers
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PRI_15
rw |
PRI_14
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler control and state register
Offset: 0x24, reset: 0x00000000, access: read-write
0/14 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
|||||
Configurable fault status register
Offset: 0x28, reset: 0x00000000, access: read-write
0/18 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
IACCVIOL
rw |
||||
Hard fault status register
Offset: 0x2c, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DEBUG_VT
rw |
FORCED
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VECTTBL
rw |
|||||||||||||||
Memory management fault address register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MMFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMFAR
rw |
|||||||||||||||
Bus fault address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BFAR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BFAR
rw |
|||||||||||||||
Auxiliary fault status register
Offset: 0x3c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IMPDEF
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IMPDEF
rw |
|||||||||||||||
0xe000e008: System control block ACTLR
0/5 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ACTRL |
Auxiliary control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DISOOFP
rw |
DISFPCA
rw |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
|||||||||||
0x40013000: Serial peripheral interface
45/45 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
data register
Offset: 0xc, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40003800: Serial peripheral interface
45/45 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
data register
Offset: 0xc, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0x40015000: Serial peripheral interface
45/45 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
data register
Offset: 0xc, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RxCRC
r |
|||||||||||||||
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TxCRC
r |
|||||||||||||||
I2S prescaler register
Offset: 0x20, reset: 00000010, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
0xe000e010: SysTick timer
0/9 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CTRL | ||||||||||||||||||||||||||||||||
| 0x4 | LOAD | ||||||||||||||||||||||||||||||||
| 0x8 | VAL | ||||||||||||||||||||||||||||||||
| 0xc | CALIB | ||||||||||||||||||||||||||||||||
SysTick control and status register
Offset: 0x0, reset: 0X00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
COUNTFLAG
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CLKSOURCE
rw |
TICKINT
rw |
ENABLE
rw |
|||||||||||||
SysTick reload value register
Offset: 0x4, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RELOAD
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RELOAD
rw |
|||||||||||||||
SysTick current value register
Offset: 0x8, reset: 0X00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CURRENT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CURRENT
rw |
|||||||||||||||
SysTick calibration value register
Offset: 0xc, reset: 0X00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NOREF
rw |
SKEW
rw |
TENMS
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TENMS
rw |
|||||||||||||||
0x40013800: System configuration controller
2/22 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MEMRM | ||||||||||||||||||||||||||||||||
| 0x4 | PMC | ||||||||||||||||||||||||||||||||
| 0x8 | EXTICR1 | ||||||||||||||||||||||||||||||||
| 0xc | EXTICR2 | ||||||||||||||||||||||||||||||||
| 0x10 | EXTICR3 | ||||||||||||||||||||||||||||||||
| 0x14 | EXTICR4 | ||||||||||||||||||||||||||||||||
| 0x20 | CMPCR | ||||||||||||||||||||||||||||||||
| 0x2c | CFGR | ||||||||||||||||||||||||||||||||
memory remap register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MEM_MODE
rw |
|||||||||||||||
peripheral mode configuration register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADC1DC2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
external interrupt configuration register 1
Offset: 0x8, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI3
rw |
EXTI2
rw |
EXTI1
rw |
EXTI0
rw |
||||||||||||
external interrupt configuration register 2
Offset: 0xc, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI7
rw |
EXTI6
rw |
EXTI5
rw |
EXTI4
rw |
||||||||||||
external interrupt configuration register 3
Offset: 0x10, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI11
rw |
EXTI10
rw |
EXTI9
rw |
EXTI8
rw |
||||||||||||
external interrupt configuration register 4
Offset: 0x14, reset: 0x0000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI15
rw |
EXTI14
rw |
EXTI13
rw |
EXTI12
rw |
||||||||||||
Compensation cell control register
Offset: 0x20, reset: 0x00000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
READY
r |
CMP_PD
r |
||||||||||||||
Configuration register
Offset: 0x2c, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FMPI2C1_SDA
rw |
FMPI2C1_SCL
rw |
||||||||||||||
0x40010000: Advanced-timers
80/127 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/12 fields covered.
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: Output Compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: Output Compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40014800: General-purpose-timers
10/27 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x50 | OR | ||||||||||||||||||||||||||||||||
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OC1M
rw |
OC1PE
rw |
OC1FE
rw |
CC1S
rw |
||||||||||||
Bits 4-6: Output Compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
option register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RMP
rw |
|||||||||||||||
0x40000c00: General-purpose-timers
77/101 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: OC1M.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: OC2M.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: OC3M.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: OC4M.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM5 option register
Offset: 0x50, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IT4_RMP
rw |
|||||||||||||||
0x40001000: Basic timers
13/13 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40010400: Advanced-timers
80/127 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
| 0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
| 0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/12 fields covered.
Bits 4-6: Master mode selection.
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode selection.
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: Output Compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: Output Compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x3c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x40, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
0x40014000: General purpose timers
12/49 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
| 0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MSM
rw |
TS
rw |
SMS
rw |
|||||||||||||
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIE
rw |
CC2IE
rw |
CC1IE
rw |
UIE
rw |
||||||||||||
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TG
w |
CC2G
w |
CC1G
w |
UG
w |
||||||||||||
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
2/8 fields covered.
Bits 4-6: Output Compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bits 12-14: Output Compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
capture/compare register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR
rw |
|||||||||||||||
0x40011000: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | SR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | BRR | ||||||||||||||||||||||||||||||||
| 0xc | CR1 | ||||||||||||||||||||||||||||||||
| 0x10 | CR2 | ||||||||||||||||||||||||||||||||
| 0x14 | CR3 | ||||||||||||||||||||||||||||||||
| 0x18 | GTPR | ||||||||||||||||||||||||||||||||
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40004400: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | SR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | BRR | ||||||||||||||||||||||||||||||||
| 0xc | CR1 | ||||||||||||||||||||||||||||||||
| 0x10 | CR2 | ||||||||||||||||||||||||||||||||
| 0x14 | CR3 | ||||||||||||||||||||||||||||||||
| 0x18 | GTPR | ||||||||||||||||||||||||||||||||
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40011400: Universal synchronous asynchronous receiver transmitter
44/51 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | SR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | BRR | ||||||||||||||||||||||||||||||||
| 0xc | CR1 | ||||||||||||||||||||||||||||||||
| 0x10 | CR2 | ||||||||||||||||||||||||||||||||
| 0x14 | CR3 | ||||||||||||||||||||||||||||||||
| 0x18 | GTPR | ||||||||||||||||||||||||||||||||
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Baud rate register
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DIV_Mantissa
rw |
DIV_Fraction
rw |
||||||||||||||
Guard time and prescaler register
Offset: 0x18, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
0x40002c00: Window watchdog
6/6 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CFR | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
Control register
Offset: 0x0, reset: 0x7F, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDGA
rw |
T
rw |
||||||||||||||
Configuration register
Offset: 0x4, reset: 0x7F, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWI
rw |
WDGTB
rw |
W
rw |
|||||||||||||
Status register
Offset: 0x8, reset: 0x00, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWIF
rw |
|||||||||||||||